1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same. In particular, the invention is suitably applied to a method for forming a field-effect transistor having a backgate electrode.
2. Related Art
Much attention is given to the usefulness of a field-effect transistor formed on a silicon-on-insulator (SOI) substrate due to the easiness of device separation, latch-up free operation, a small amount of source and drain junction capacitance and the like. In particular, a fully-depleted SOI transistor can exhibit low power consumption and high-speed performance, while operating at low voltage. Accordingly, research has been actively conducted to develop SOI transistors operating in a fully-depleted mode. In this case, an SOI substrate is formed of, for example, a separation by implanted oxygen (SIMOX) substrate, a bonding substrate or the like, as disclosed in first and second patent examples of related art provided below.
Additionally, a previous semiconductor device manufacturing method has provided a field-effect transistor having a high breakdown voltage, in which a backgate electrode is formed on an insulating film covering the field-effect transistor and connected to a gate or a source, as described in third and fourth patent examples of the related art below.
Furthermore, a non-patent example of the related art below has disclosed a method for forming an SOI transistor at a low cost by forming an SOI layer on a bulk substrate. In this method, Si/SiGe layers are film-formed on an Si substrate and only the SiGe layer is selectively removed by taking advantage of a difference in etch selectivity ratio between Si and SiGe. Thereby, a cavity is formed between the Si substrate and the Si layer. Then, thermal oxidation of Si exposed in the cavity is performed to bury an SiO2 layer between the Si substrate and the Si layer, whereby a buried oxide (BOX) layer is formed therebetween.
Here, in order to enable both high-speed performance and low power consumption of a field-effect transistor while attaining miniaturization thereof, there is a method for forming an SOI transistor having a backgate structure or a double gate structure.
JP-A-2002-299591 is a first example of the related art.
JP-A-2000-124092 is a second example of the related art.
JP-A-9-45909 is a third example of the related art.
JP-A-9-205211 is a fourth example of the related art.
“Separation by Bonding Si Islands (SBSI) for LSI Application” (by T. Sakai et al., Second International GiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May 2004) is a non-patent example of the related art.
In previous semiconductor integrated circuits, however, reduction in channel length due to transistor miniaturization deteriorates drain-current rising characteristics in a subthreshold region. This hinders low-voltage operation of a transistor, and increases leakage current during an off-time period thereof and its operating and standby power consumption. Moreover, the deterioration even leads to destruction of the transistor.
Furthermore, there is a problem that arrangement of a backgate electrode on an entire surface region under a field-effect transistor increases parasitic capacitance between the backgate electrode and source and drain layers, thereby hindering high-speed performance of the SOI transistor.